Control Unit

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Control Unit

The control unit is responsible for decoding the opcode and operand bits in the instruction register, and then generating the control signals necessary to drive all other hardware in the CPU to perform the sequence of micro-operations that comprise the instruction.

Design of Control Unit

The function of the control unit in a digital computer. is to initiate sequences of micro operations (the operations executed on data stored in registers are called micro operations).

• The number of different types of micro operations that are available in a given system is finite.
• When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired.
• Micro-programming is a second alternative for designing the control unit of a digital computer.

• The control unit initiates a series of sequential steps of micro operations. During any given time certain micro operations are to be initiated, while others remain idle.
• The control variables at any given time can be represented by a string of 1 s and 0 s called a control word.

Two approaches used for generating the control signals in proper sequence: Hardwired control unit and Micro-programmed control unit.

Hardwired Control

• Fixed logic circuits that correspond directly to the Boolean expressions are used to generate the control signals.
• Hardwired control is faster than microprogrammed control.
• A controller that uses this approach can operate at high speed.
• The control hardwire can be viewed as a state machine that changes from one state to another in every clock cycle, depending on the contents of the instruction register, the condition codes, and the external inputs. The outputs of the state machine are the control signals. The sequence of operations carried out by this machine is determined by the wiring of the logic elements, hence the name “hardwired”.

Micro-Programmed Control

• The control signals associated with operations are stored in special memory units inaccessible by the programmer as control words.
• Control signals are generated by a program similar to machine language programs.
• It leads to a slower operating speed because of the time it takes to fetch microinstructions from the control store.
• Control word: A control word is a word whose individual bits represent the various control signals.
• Micro-routine: A sequence of control words corresponding to the control sequence of a machine instruction constitutes the microroutine for that instruction,
• Micro-instruction: Individual control words in this microroutine are referred to as microinstructions.
• Micro-program: A sequence of microinstructions is called a microprogram, which is stored in a ROM or RAM called a control memory CM.

• Control Store: The micro-routines for all instructions in the instruction set of a computer are stored in a special memory called the control store.

Micro-instructions are commonly divided into two categories: horizontal and vertical.

Horizontal Control:

Each micro-instruction is a series of bits each of which represents a single control line.

Horizontal micro-instructions are characterized by:

• Long formats;
• Ability to express a high degree of parallelism;
• Minimally encoded scheme
• Many resources can be controlled
• Operating speed is low

Vertical Control

Groups of bits in the micro-instruction represent commands. This requires decoding or de-multiplexing before the control commands can be issued.

Vertical micro-instructions are characterized by:

• Short formats;
• Limited ability to express microoperation parallelism;
• Highly encoded schemes, hence considerable lightly encoded.
• Operating speed is high

Horizontal microinstruction control is faster but requires greater length microinstructions.

Operations:

Instruction Fetch Step: Read into Instruction Register from Memory at address indicated by Program Counter register. Then increment program counter to point to the next instruction.

IR <= InstrCache[PC];

PC <= PC + 4;

Instruction Decode and Register Read Step:

RS <= RegFile[IR[25:21]];

RT <= RegFile[IR[20:16]];

Immediate <= sign-extend(IR[15:0]);

pcALUOut <= PC + (Immediate << 2);

ALU Operation:

This is instruction-specific, since control knows the instruction type.

R-Type Instruction: ALUOut <= RS op RT

Memory-Reference Instr: ALUOut <= RS + Immediate

Branch Instruction: If (RS/x compare RT/y) PC <= ALUOut

Jump Instruction: PC <= (PC(31:28), (IR[25:0],2*b00))

Data Cache Access

R-Type Instruction: RegFile[IR[15:11]] <= ALUOut

Memory-Reference Instr:

Load Instr: DataCacheOut <= DataCache[ALUOut]

Store Instr: DataCache[ALUOut] <=RT/Y

Register Write-Back

Load Instr: RegFile[IR[20:16]] <= DataCacheOut

Fetch Instruction:

The following sequence of events in fetching an instruction:

1. The contents of the PC are loaded into the MAR.
2. The value in the PC is incremented. (This operation can be done in parallel with a memory access.)
3. As a result of a memory read operation, the instruction is loaded into the MDR.
4. The contents of the MDR are loaded into the IR.

Using Single Bus Data Path:

Using Three Bus Data Path:

Execution of an Instruction:

Simple Arithmetic Operation: Add R1, R2, R0

This instruction adds the contents of source registers R1 and R2, and stores the results in destination register R0.

This addition can be executed as in the following sequence:

1. The registers R0 , R1 , R2 , are extracted from the IR.
2. The contents of R1 and R2 are passed to the ALU for addition.
3. The output of the ALU is transferred to R0 .

Using Single Bus Datapath:

Using Two Bus Datapath:

Using Three Bus Datapath:

Fetching a Word from Memory

1. MAR ← [R1]
2. Request memory READ and put the data to the address register
3. Wait for the Memory Fetch Cycle (MFC) signal and put the result from [MDR] to R2.
4. R2 ←[MDR]

Storing a Word in Memory

1. MAR ← [R1]
2. MDR ←[R2]
3. Request memory write
4. Wait for MFC signal

Interrupt Handling

After the execution of an instruction, a test is performed to check for pending interrupts. If there is an interrupt request waiting, the following sequence of steps take place:

1. The contents of PC are loaded into MDR (to be saved).
2. The MAR is loaded with the address at which the PC contents are to be saved.
3. The PC is loaded with the address of the first instruction of the interrupt handling routine.
4. The contents of MDR (old value of the PC) are stored in memory.

Regards
Amrut Jagdish Gupta